Designers can now harness computing power through the web from cloud resources to take full advantage of Tabula's breakthrough Spacetime 3D architecture, accelerating end-product time-to-market at lower costs. The industry's first integrated synthesis and place-and-route (SP&R) package supporting 3PLD devices, Stylus manages the underlying reconfiguration transparently, automatically mapping standard RTL into Spacetime.
LTE, EPC, WiMAX, 4G Wireless Backhaul
40G/100G Ethernet
Carrier-Grade Ethernet
Fixed Mobile Convergence
Video Networks and IPTV
Accelerate Production
Communications equipment vendors developing solutions for next generation networks require a flexible platform with high performance capability. In addition, they need to get to market quickly and keep costs down. With Tabula's ABAX™ product family, equipment suppliers now have access to a tehnologically advanced platform that delivers superior compute power at competitive price points.
COMPANY FAST FACTS:
Founded: 2003
Founded by EDA pioneer, Steve Teig
100+ employees
120+ patents granted
CORPORATE HEADQUARTERS:
3250 Olcott St.
Santa Clara, CA 95054
Phone: (408) 986-9140
Fax: (408) 986-9146
ANALYST, PRESS INQUIRES:
Sabrina Joseph, Managing Partner Morphoses
560 S. Winchester Blvd., Suite 500
San Jose, CA 95128
Tel: (408)236-7373 tabulapr@morphoses.com
Electronic systems manufacturers have always wanted to bring innovative, large-scale designs to market quickly while keeping unit costs low. Addressing this daunting, unmet need requires a scalable, programmable platform: one that can be used from the first explorations of a new idea all the way through volume production. Current programmable devices, such as FPGAs, fail to meet this need because they are simply too large to be cost-effective in most production settings.
Tabula's ABAX™ family of 3D Programmable Logic Devices (3PLD) represents a new category of general-purpose chips. Leveraging Tabula's breakthrough Spacetime™ architecture, ABAX delivers programmability with unprecedented capabilities at volume price points. Setting new marks in density and performance for logic, memory, and signal processing, ABAX extends the benefits of programmability to many applications that previously required ASICs or ASSPs. In addition, ABAX devices have a rich mixture of fully configurable, high-performance I/Os, including 920 general-purpose I/Os and 48 6.5Gbps SerDes. The design flow is similar to FPGA and ASIC flows; using synthesis, placement, and routing to compile designs from RTL into silicon automatically. To increase designers' productivity, ABAX also supports a broad portfolio of soft IP cores.
To simplify system design evolution and upgrade, all the devices in the ABAX family share a common footprint and pinout, enabling vertical migration.
CONFIGURABLE I/O
To enable greater flexibility and ease of system design, ABAX devices' parallel I/O and SerDes are fully programmable and support a broad range of standards
PARALLEL I/O
Each ABAX device has 920 fully featured General Purpose I/O (GPIO)
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Fully configurable to support a broad range of standards
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Per bit de-skew
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Built-in hardware for clock control between Spacetime fabric and I/O
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Dedicated support for DDR standards
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Hardware-assisted read/write leveling
PARALLEL I/O
STANDARD
PERFORMANCE (MHz)
DDR (Mb/s) PERFORMANCE
3.0V, 2.5V, 1.8V, 1.5V LVTTL/LVCMOS
General purpose
200
400
SSTL-2 Class I, II
DDRSDRAM
200
400
SSTL-18 Class I, II
DDR2 SDRAM
400
800
SSTL-15
DDR3 SDRAM
400
800
HSTL-18 Class I, II
QDRII/QDRII+/RLDRAM II
400
800
HSTL-15 Class I, II
QDRII/QDRII+/RLDRAM II
400
800
Diff SSTL-2 Class I, II
DDR SDRAM
200
400
Diff SSTL-18 Class I, II
DDR2 SDRAM
400
800
Diff SSTL-15
DDR3 SDRAM
400
800
Diff HSTL-18 Class I, II
Clock interfaces
400
800
Diff HSTL-15 Class I, II
Clock interfaces
400
800
LVDS
High-speed comm.
600
1200
RSDS & Mini-LVDS
Flat panel display
85
170
HyperTransport
μP bus/router/switch
600
1200
LVPECL
Clock interfaces
450
900
Open Drain
General purpose
-
-
SerDes
Each ABAX device has 48 SerDes
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55 Mbps - 6.5 Gbps operation
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Built-in PMA and PCS per SerDes channel
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Fully programmable PMA and PCS
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Independent clocking per channel
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Channel bond: 2-24 channels
SerDes STANDARDS
DATA RATE (Gbps)
PCI Express Gen1 and Gen2
2.5, 5
GbE/SGMII
1.25
XAUI/RXAUI
3.125, 6.25
Interlaken
3.125-6.375
GPON
1.244, 2.488
Serial RapidIO
1.25, 2.5, 3.125, 6.25
CPRI LV
0.614, 1.228, 2.457, 3.072, 6.144
OBSAI
0.768, 1.536, 3.072, 6.144
Sonet
0.155, 0.622, 2.488
SMPTE SD/HD
0.270, 1.485, 2.97
DisplayPort
1.62, 2.7, 5.4
Fibre Channel
1.06, 2.12, 4.25
SATA/SAS
1.5, 3.0, 6.0
DVB-ASI
0.270
JC-16
0.3125-3.125
OIF SPI-S/SFI-5
3.125
EMBEDDED MEMORY
Each ABAX product integrates 5.5 MBYTES of 8- and 16-port configurable user RAM
RAM blocks come in three sizes to support various use models. They are
configurable in width and depth to accommodate different data sizes
8- and 16-ported memories
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Ultra-high memory bandwidth
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High utilization of memory resources, even when data size and RAM block size do not match
Memory mapping and multi-port memory generation are automatically managed
by the Spacetime compiler
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Simple to use; no additional user logic required
LRAM (Large RAM)
MRAM (Medium RAM)
RegFILE
Block Size
72Kb
36Kb
576b
Ports
Up to 8
Up to 16
Up to 16
Configuration
36Kx2/ 18Kx4/ 9Kx8/ 4Kx16/ 9Kx9/ 4Kx18/td>
18Kx2 /9Kx4/ 4Kx8/ 2Kx16/ 4Kx9/ 2Kx18
9 x 64
Access
Synchronous
Synchronous
Synchronous Write/ Asynchronous Read
Features
ECC
ECC, Built-in FIFO controller with programmable watermark
Usable as a 6-LUT
STYLUS SPACETIME COMPILER
The Spacetime architecture is designed to work with your existing design methodology. Therefore, there is no need to change or adapt your design environment to accommodate its 3-D nature
The Stylus Spacetime compiler automatically maps, places, and routes your design into an ABAX device using standard design inputs and flows
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Verilog/VHDL input
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An intuitive GUI to manage design inputs, projects, and design flows
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SDC timing constraints and Tcl-based pin and placement constraints
All control of the hardware reconfiguration is automatically and transparently managed by the Spacetime compiler
MACRO LIBRARY
To facilitate the use of ABAX devices' rich on-chip resources, Tabula has developed a library of fully validated macros delivering functionality for:
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Parameterized multi-port memories
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General- and special-purpose I/O interfaces
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Standard and custom SerDes protocols
THIRD-PARTY SOFT IP
To increase designers' productivity, Tabula is working with leading third-party soft IP suppliers to offer a broad portfolio of high-quality soft IP solutions, including:
